{"id":2143,"date":"2026-04-21T02:08:10","date_gmt":"2026-04-21T02:08:10","guid":{"rendered":"https:\/\/aijaps.us\/?p=2143"},"modified":"2026-04-21T02:08:10","modified_gmt":"2026-04-21T02:08:10","slug":"doherty-power-amplifiers-in-cmos-technology-for-5g-millimetre-wave-applications-architectures-design-techniques-and-performance-trade-offs","status":"publish","type":"post","link":"https:\/\/aijaps.us\/?p=2143","title":{"rendered":"Doherty Power Amplifiers in CMOS Technology for 5G Millimetre-Wave Applications: Architectures, Design Techniques, and Performance Trade-offs"},"content":{"rendered":"

Abdulmunam Abtan1\u207b2<\/sup><\/strong><\/h3>\n

1<\/sup><\/strong>Scientific Research Commission, Higher Education and Scientific Research Ministry, Baghdad, Iraq<\/strong><\/h3>\n

2<\/sup><\/strong>Electronic, <\/strong>Electrical & Computer Engineering<\/strong>, <\/strong>University of Tabriz<\/strong>, <\/strong>Tabriz<\/strong>, <\/strong>Iran<\/strong><\/h3>\n

Email:<\/strong>munam.net@gmail.com.<\/strong><\/h3>\n

Abdulmunam.o.abtan@src.edu.iq<\/strong><\/a><\/h3>\n

Phone Number:+9647800635454<\/strong><\/h3>\n

Sirous Toofan2<\/sup><\/strong><\/h3>\n

2<\/sup><\/strong>Electronic, <\/strong>Electrical & Computer Engineering<\/strong>, <\/strong>University of Tabriz<\/strong>, <\/strong>Tabriz<\/strong>, <\/strong>Iran<\/strong><\/h3>\n

Email: <\/strong>s.toofan@tabrizu.ac.ir<\/strong><\/h3>\n

Phone Number:+989125948476<\/strong><\/h3>\n

Ziaddin Daie Kuzekan2<\/sup><\/strong><\/h3>\n

2<\/sup><\/strong>Electronic, <\/strong>Electrical & Computer Engineering<\/strong>, <\/strong>University of Tabriz<\/strong>, <\/strong>Tabriz<\/strong>, <\/strong>Iran<\/strong><\/h3>\n

Email: <\/strong>zdaie@tabrizu.ac.ir<\/strong><\/h3>\n

\u00a0
Abdulmunam Abtan<\/a><\/div><\/strong><\/h3>\n","protected":false},"excerpt":{"rendered":"

Abdulmunam Abtan1\u207b2 1Scientific Research Commission, Higher Education and Scientific Research Ministry, Baghdad, Iraq 2Electronic, Electrical…<\/p>\n","protected":false},"author":1,"featured_media":2145,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1,45],"tags":[],"class_list":["post-2143","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-uncategorized","category-45"],"yoast_head":"\nDoherty Power Amplifiers in CMOS Technology for 5G Millimetre-Wave Applications: Architectures, Design Techniques, and Performance Trade-offs - aijaps<\/title>\n<meta name=\"description\" content=\"Abstract: Fifth-generation (5G) wireless networks in the millimetre-wave (mm-wave) frequency range have proliferated rapidly and placed demanding and simultaneous requirements on the RF power amplifiers (PAs), such as high power-added efficiency (PAE), sufficient output power, good linearity, and wide instantaneous bandwidth. The current power amplifier architectures are not ideal; therefore, active load modulation for the Doherty Power Amplifier (DPA) can be considered the most suitable alternative by balancing all competing demands that may arise from complementary metal-oxide semiconductor (CMOS) technology. This study provides an abstract and rigorous analysis of all DPA designs, including the CMOS architecture for the 5G FR2 frequency assignment (24\u201343 GHz), and the results of the 17 selected CMOS schemes are from 2022 to 2026. These areas review: (i) technology-node trade-offs from bulk CMOS (90\u201328 nm), RF silicon-on-insulator (RF-SOI), and fully depleted SOI (FD-SOI) platforms; (ii) major paradigms regarding DPA architecture (two-way, N-way, series-Doherty; quasi-balanced; transformer-combined topologies); and (iii) detailed quantitative comparison of key performance statistics\u2014saturated output power (P\u209b\u2090\u209c), peak power-added efficiency (PAE\u209a\u2091\u2090\u2096 up to 38.2%), back-off PAE at 6 dB (PAE\u2086\u1d48\u1d2e up to 34.5%), small-signal gain, and operating bandwidth. The results of this study reveal four primary design challenges: low transistor breakdown voltage; frequency-dependent passive component losses (Q = 10\u201320) for bulk CMOS; linearity decay due to a high peak-to-average power ratio (PAPR) signal; and the complexity of multi-way power combining. To meet these constraints, the authors propose five main research directions: exploitation of sophisticated CMOS nodes and SOI substrates, hybrid N-way combining architectures, co-designed adaptive bias and digital predistortion, ultra-wideband load modulation networks, and extension of the Doherty principle to the sub-terahertz (sub-THz) region for 6G. The results are intended to serve as a structured reference for researchers and engineers involved in mm-wave CMOS front-end design. Keywords: Doherty power amplifier; CMOS technology; 5G mm-wave; Power-added efficiency; Active load modulation; Transformer combining.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/aijaps.us\/?p=2143\" \/>\n<meta property=\"og:locale\" content=\"ar_AR\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Doherty Power Amplifiers in CMOS Technology for 5G Millimetre-Wave Applications: Architectures, Design Techniques, and Performance Trade-offs - aijaps\" \/>\n<meta property=\"og:description\" content=\"Abstract: Fifth-generation (5G) wireless networks in the millimetre-wave (mm-wave) frequency range have proliferated rapidly and placed demanding and simultaneous requirements on the RF power amplifiers (PAs), such as high power-added efficiency (PAE), sufficient output power, good linearity, and wide instantaneous bandwidth. The current power amplifier architectures are not ideal; therefore, active load modulation for the Doherty Power Amplifier (DPA) can be considered the most suitable alternative by balancing all competing demands that may arise from complementary metal-oxide semiconductor (CMOS) technology. This study provides an abstract and rigorous analysis of all DPA designs, including the CMOS architecture for the 5G FR2 frequency assignment (24\u201343 GHz), and the results of the 17 selected CMOS schemes are from 2022 to 2026. These areas review: (i) technology-node trade-offs from bulk CMOS (90\u201328 nm), RF silicon-on-insulator (RF-SOI), and fully depleted SOI (FD-SOI) platforms; (ii) major paradigms regarding DPA architecture (two-way, N-way, series-Doherty; quasi-balanced; transformer-combined topologies); and (iii) detailed quantitative comparison of key performance statistics\u2014saturated output power (P\u209b\u2090\u209c), peak power-added efficiency (PAE\u209a\u2091\u2090\u2096 up to 38.2%), back-off PAE at 6 dB (PAE\u2086\u1d48\u1d2e up to 34.5%), small-signal gain, and operating bandwidth. The results of this study reveal four primary design challenges: low transistor breakdown voltage; frequency-dependent passive component losses (Q = 10\u201320) for bulk CMOS; linearity decay due to a high peak-to-average power ratio (PAPR) signal; and the complexity of multi-way power combining. To meet these constraints, the authors propose five main research directions: exploitation of sophisticated CMOS nodes and SOI substrates, hybrid N-way combining architectures, co-designed adaptive bias and digital predistortion, ultra-wideband load modulation networks, and extension of the Doherty principle to the sub-terahertz (sub-THz) region for 6G. The results are intended to serve as a structured reference for researchers and engineers involved in mm-wave CMOS front-end design. Keywords: Doherty power amplifier; CMOS technology; 5G mm-wave; Power-added efficiency; Active load modulation; Transformer combining.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/aijaps.us\/?p=2143\" \/>\n<meta property=\"og:site_name\" content=\"aijaps\" \/>\n<meta property=\"article:published_time\" content=\"2026-04-21T02:08:10+00:00\" \/>\n<meta property=\"og:image\" content=\"http:\/\/aijaps.us\/wp-content\/uploads\/2026\/04\/2.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"1280\" \/>\n\t<meta property=\"og:image:height\" content=\"720\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"aijaps.us\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"\u0643\u064f\u062a\u0628 \u0628\u0648\u0627\u0633\u0637\u0629\" \/>\n\t<meta name=\"twitter:data1\" content=\"aijaps.us\" \/>\n\t<meta name=\"twitter:label2\" content=\"\u0648\u0642\u062a \u0627\u0644\u0642\u0631\u0627\u0621\u0629 \u0627\u0644\u0645\u064f\u0642\u062f\u0651\u0631\" \/>\n\t<meta name=\"twitter:data2\" content=\"\u062f\u0642\u064a\u0642\u0629 \u0648\u0627\u062d\u062f\u0629\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/aijaps.us\\\/?p=2143#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/aijaps.us\\\/?p=2143\"},\"author\":{\"name\":\"aijaps.us\",\"@id\":\"https:\\\/\\\/aijaps.us\\\/#\\\/schema\\\/person\\\/e0e97926a8d995bc1e65a0f9ac22f991\"},\"headline\":\"Doherty Power Amplifiers in CMOS Technology for 5G Millimetre-Wave Applications: Architectures, Design Techniques, and Performance Trade-offs\",\"datePublished\":\"2026-04-21T02:08:10+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/aijaps.us\\\/?p=2143\"},\"wordCount\":102,\"commentCount\":0,\"publisher\":{\"@id\":\"https:\\\/\\\/aijaps.us\\\/#organization\"},\"image\":{\"@id\":\"https:\\\/\\\/aijaps.us\\\/?p=2143#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/aijaps.us\\\/wp-content\\\/uploads\\\/2026\\\/04\\\/2.jpg\",\"articleSection\":[\"Uncategorized\",\"\u0627\u0635\u062f\u0627\u0631\u0627\u062a \u0627\u0644\u0628\u062d\u0648\u062b\"],\"inLanguage\":\"ar\",\"potentialAction\":[{\"@type\":\"CommentAction\",\"name\":\"Comment\",\"target\":[\"https:\\\/\\\/aijaps.us\\\/?p=2143#respond\"]}]},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/aijaps.us\\\/?p=2143\",\"url\":\"https:\\\/\\\/aijaps.us\\\/?p=2143\",\"name\":\"Doherty Power Amplifiers in CMOS Technology for 5G Millimetre-Wave Applications: Architectures, Design Techniques, and Performance Trade-offs - aijaps\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/aijaps.us\\\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\\\/\\\/aijaps.us\\\/?p=2143#primaryimage\"},\"image\":{\"@id\":\"https:\\\/\\\/aijaps.us\\\/?p=2143#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/aijaps.us\\\/wp-content\\\/uploads\\\/2026\\\/04\\\/2.jpg\",\"datePublished\":\"2026-04-21T02:08:10+00:00\",\"description\":\"Abstract: Fifth-generation (5G) wireless networks in the millimetre-wave (mm-wave) frequency range have proliferated rapidly and placed demanding and simultaneous requirements on the RF power amplifiers (PAs), such as high power-added efficiency (PAE), sufficient output power, good linearity, and wide instantaneous bandwidth. The current power amplifier architectures are not ideal; therefore, active load modulation for the Doherty Power Amplifier (DPA) can be considered the most suitable alternative by balancing all competing demands that may arise from complementary metal-oxide semiconductor (CMOS) technology. This study provides an abstract and rigorous analysis of all DPA designs, including the CMOS architecture for the 5G FR2 frequency assignment (24\u201343 GHz), and the results of the 17 selected CMOS schemes are from 2022 to 2026. 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To meet these constraints, the authors propose five main research directions: exploitation of sophisticated CMOS nodes and SOI substrates, hybrid N-way combining architectures, co-designed adaptive bias and digital predistortion, ultra-wideband load modulation networks, and extension of the Doherty principle to the sub-terahertz (sub-THz) region for 6G. The results are intended to serve as a structured reference for researchers and engineers involved in mm-wave CMOS front-end design. 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The current power amplifier architectures are not ideal; therefore, active load modulation for the Doherty Power Amplifier (DPA) can be considered the most suitable alternative by balancing all competing demands that may arise from complementary metal-oxide semiconductor (CMOS) technology. This study provides an abstract and rigorous analysis of all DPA designs, including the CMOS architecture for the 5G FR2 frequency assignment (24\u201343 GHz), and the results of the 17 selected CMOS schemes are from 2022 to 2026. These areas review: (i) technology-node trade-offs from bulk CMOS (90\u201328 nm), RF silicon-on-insulator (RF-SOI), and fully depleted SOI (FD-SOI) platforms; (ii) major paradigms regarding DPA architecture (two-way, N-way, series-Doherty; quasi-balanced; transformer-combined topologies); and (iii) detailed quantitative comparison of key performance statistics\u2014saturated output power (P\u209b\u2090\u209c), peak power-added efficiency (PAE\u209a\u2091\u2090\u2096 up to 38.2%), back-off PAE at 6 dB (PAE\u2086\u1d48\u1d2e up to 34.5%), small-signal gain, and operating bandwidth. The results of this study reveal four primary design challenges: low transistor breakdown voltage; frequency-dependent passive component losses (Q = 10\u201320) for bulk CMOS; linearity decay due to a high peak-to-average power ratio (PAPR) signal; and the complexity of multi-way power combining. To meet these constraints, the authors propose five main research directions: exploitation of sophisticated CMOS nodes and SOI substrates, hybrid N-way combining architectures, co-designed adaptive bias and digital predistortion, ultra-wideband load modulation networks, and extension of the Doherty principle to the sub-terahertz (sub-THz) region for 6G. The results are intended to serve as a structured reference for researchers and engineers involved in mm-wave CMOS front-end design. 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The current power amplifier architectures are not ideal; therefore, active load modulation for the Doherty Power Amplifier (DPA) can be considered the most suitable alternative by balancing all competing demands that may arise from complementary metal-oxide semiconductor (CMOS) technology. This study provides an abstract and rigorous analysis of all DPA designs, including the CMOS architecture for the 5G FR2 frequency assignment (24\u201343 GHz), and the results of the 17 selected CMOS schemes are from 2022 to 2026. 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Keywords: Doherty power amplifier; CMOS technology; 5G mm-wave; Power-added efficiency; Active load modulation; Transformer combining.","og_url":"https:\/\/aijaps.us\/?p=2143","og_site_name":"aijaps","article_published_time":"2026-04-21T02:08:10+00:00","og_image":[{"width":1280,"height":720,"url":"http:\/\/aijaps.us\/wp-content\/uploads\/2026\/04\/2.jpg","type":"image\/jpeg"}],"author":"aijaps.us","twitter_card":"summary_large_image","twitter_misc":{"\u0643\u064f\u062a\u0628 \u0628\u0648\u0627\u0633\u0637\u0629":"aijaps.us","\u0648\u0642\u062a \u0627\u0644\u0642\u0631\u0627\u0621\u0629 \u0627\u0644\u0645\u064f\u0642\u062f\u0651\u0631":"\u062f\u0642\u064a\u0642\u0629 \u0648\u0627\u062d\u062f\u0629"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/aijaps.us\/?p=2143#article","isPartOf":{"@id":"https:\/\/aijaps.us\/?p=2143"},"author":{"name":"aijaps.us","@id":"https:\/\/aijaps.us\/#\/schema\/person\/e0e97926a8d995bc1e65a0f9ac22f991"},"headline":"Doherty Power Amplifiers in CMOS Technology for 5G Millimetre-Wave Applications: Architectures, Design Techniques, and Performance Trade-offs","datePublished":"2026-04-21T02:08:10+00:00","mainEntityOfPage":{"@id":"https:\/\/aijaps.us\/?p=2143"},"wordCount":102,"commentCount":0,"publisher":{"@id":"https:\/\/aijaps.us\/#organization"},"image":{"@id":"https:\/\/aijaps.us\/?p=2143#primaryimage"},"thumbnailUrl":"https:\/\/aijaps.us\/wp-content\/uploads\/2026\/04\/2.jpg","articleSection":["Uncategorized","\u0627\u0635\u062f\u0627\u0631\u0627\u062a \u0627\u0644\u0628\u062d\u0648\u062b"],"inLanguage":"ar","potentialAction":[{"@type":"CommentAction","name":"Comment","target":["https:\/\/aijaps.us\/?p=2143#respond"]}]},{"@type":"WebPage","@id":"https:\/\/aijaps.us\/?p=2143","url":"https:\/\/aijaps.us\/?p=2143","name":"Doherty Power Amplifiers in CMOS Technology for 5G Millimetre-Wave Applications: Architectures, Design Techniques, and Performance Trade-offs - aijaps","isPartOf":{"@id":"https:\/\/aijaps.us\/#website"},"primaryImageOfPage":{"@id":"https:\/\/aijaps.us\/?p=2143#primaryimage"},"image":{"@id":"https:\/\/aijaps.us\/?p=2143#primaryimage"},"thumbnailUrl":"https:\/\/aijaps.us\/wp-content\/uploads\/2026\/04\/2.jpg","datePublished":"2026-04-21T02:08:10+00:00","description":"Abstract: Fifth-generation (5G) wireless networks in the millimetre-wave (mm-wave) frequency range have proliferated rapidly and placed demanding and simultaneous requirements on the RF power amplifiers (PAs), such as high power-added efficiency (PAE), sufficient output power, good linearity, and wide instantaneous bandwidth. The current power amplifier architectures are not ideal; therefore, active load modulation for the Doherty Power Amplifier (DPA) can be considered the most suitable alternative by balancing all competing demands that may arise from complementary metal-oxide semiconductor (CMOS) technology. This study provides an abstract and rigorous analysis of all DPA designs, including the CMOS architecture for the 5G FR2 frequency assignment (24\u201343 GHz), and the results of the 17 selected CMOS schemes are from 2022 to 2026. These areas review: (i) technology-node trade-offs from bulk CMOS (90\u201328 nm), RF silicon-on-insulator (RF-SOI), and fully depleted SOI (FD-SOI) platforms; (ii) major paradigms regarding DPA architecture (two-way, N-way, series-Doherty; quasi-balanced; transformer-combined topologies); and (iii) detailed quantitative comparison of key performance statistics\u2014saturated output power (P\u209b\u2090\u209c), peak power-added efficiency (PAE\u209a\u2091\u2090\u2096 up to 38.2%), back-off PAE at 6 dB (PAE\u2086\u1d48\u1d2e up to 34.5%), small-signal gain, and operating bandwidth. The results of this study reveal four primary design challenges: low transistor breakdown voltage; frequency-dependent passive component losses (Q = 10\u201320) for bulk CMOS; linearity decay due to a high peak-to-average power ratio (PAPR) signal; and the complexity of multi-way power combining. To meet these constraints, the authors propose five main research directions: exploitation of sophisticated CMOS nodes and SOI substrates, hybrid N-way combining architectures, co-designed adaptive bias and digital predistortion, ultra-wideband load modulation networks, and extension of the Doherty principle to the sub-terahertz (sub-THz) region for 6G. The results are intended to serve as a structured reference for researchers and engineers involved in mm-wave CMOS front-end design. Keywords: Doherty power amplifier; CMOS technology; 5G mm-wave; Power-added efficiency; Active load modulation; Transformer combining.","breadcrumb":{"@id":"https:\/\/aijaps.us\/?p=2143#breadcrumb"},"inLanguage":"ar","potentialAction":[{"@type":"ReadAction","target":["https:\/\/aijaps.us\/?p=2143"]}]},{"@type":"ImageObject","inLanguage":"ar","@id":"https:\/\/aijaps.us\/?p=2143#primaryimage","url":"https:\/\/aijaps.us\/wp-content\/uploads\/2026\/04\/2.jpg","contentUrl":"https:\/\/aijaps.us\/wp-content\/uploads\/2026\/04\/2.jpg","width":1280,"height":720},{"@type":"BreadcrumbList","@id":"https:\/\/aijaps.us\/?p=2143#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"\u0627\u0644\u0631\u0626\u064a\u0633\u064a\u0629","item":"https:\/\/aijaps.us\/"},{"@type":"ListItem","position":2,"name":"Doherty Power Amplifiers in CMOS Technology for 5G Millimetre-Wave Applications: Architectures, Design Techniques, and Performance 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